iChip is the first open-source CI/CD platform that unifies RISC-V chip design, RTL verification, and QEMU software deployment into one automated pipeline — triggered by a single git push.
Each stage produces versioned, SHA-256-hashed artifacts consumed by the next. Every stage is independently re-runnable and fully observable.
Push Verilog or Chisel. OpenLane 2 runs synthesis, place-and-route, DRC, and LVS automatically. Design metrics — area, timing slack, cell count, power estimate — are captured as JSON artifacts. GitHub Check reports pass/fail within 60 minutes.
Layer 1: lint + directed tests (~5 min) on every PR. Layer 2: riscv-arch-test ISA compliance on merge. Layer 3: 1000+ random instruction co-simulation with Verilator vs Spike step-and-compare, nightly. Layer 4: formal property checking with SymbiYosys on release gates.
iChip Cloud provides remote access to a pool of hosted FPGA boards — Xilinx ZCU102, Digilent Arty A7, and AMD VCK190. Your verified RTL is synthesised and programmed automatically. Real-silicon timing, GPIO, and peripheral behaviour are validated before any tapeout commitment.
Boot a matrix of OS images on QEMU virt plus bare-metal RISC-V nodes after every verified build. Ubuntu 24.04, Debian riscv64, Buildroot, Zephyr, FreeRTOS. Results published automatically to KernelCI. Full software stack validated end-to-end.
OpenLane, Verilator, Spike, and QEMU are mature and battle-tested. Nobody has connected them into a single, CI-native, automated workflow. That's what iChip builds.
A single git push triggers all three stages in sequence. Artifacts flow automatically with SHA-256 integrity and a full lineage DAG you can query from the CLI.
Built entirely on Apache 2.0 open-source tools. No proprietary EDA licences required. Supports SKY130, GF180MCU, and IHP-SG13G2 open PDKs.
Lightweight checks on every PR. Heavy random testing and formal verification on nightly and release builds. Fast feedback where it matters most.
Stage 3 runs on bare-metal RISC-V nodes — Scaleway EM-RV1 and RISE Runners — not just x86 QEMU. Catch silicon-specific bugs before your tapeout.
Every GDS, netlist, coverage report, and boot log is a node in a queryable DAG. Trace exactly which RTL commit produced which chip, verification, and OS boot.
Open-source projects get free compute. Aligned with RISC-V International, CHIPS Alliance, FOSSi Foundation, and the RISE Project. Upstream-first always.
From first-time chip designers to professional verification teams — iChip removes the pipeline setup burden for everyone.
Teams building CVA6, VeeR, PicoRV32, and custom cores. Currently wiring up verification manually per project. iChip gives them a standard harness in minutes, not weeks.
Academic teams who need to submit chip designs, run verification, and boot software without infrastructure teams. Publication-ready results built in.
Hobbyists and first-time designers. Automated DRC/LVS compliance testing before submission — before you spend the slot fee finding out it fails.
Early-stage teams building custom RISC-V SoCs who cannot afford Cadence or Synopsys licences. A managed, professional CI/CD pipeline at a fraction of the cost.
Every tool is battle-tested in real silicon flows. We integrate them — we don't reinvent them. Apache 2.0 all the way through.
iChip is open-source and free for public projects. Drop a ichip.yaml in your repo and go.
Everything you need to know about iChip before you get started.